1. Field of the Invention
The invention relates to testing of electronic systems generally, and more particularly to elevated temperature testing of electronic systems.
2. Background
Advances in semiconductor manufacturing technology have led to the reduction of circuit element feature sizes, which in turn has led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors (MOSFETs). MOSFETs are also commonly referred to simply as FETs.
Reduction of circuit feature sizes will reduce the associated parasitic capacitance that results in unwanted power dissipation during the operation of the integrated circuit. However, the trend to increase the number of active circuit elements and the frequency at which those circuit elements operate has resulted in integrated circuits that consume relatively large amounts of power as compared to earlier generations of integrated circuits.
A well known effect of high power consumption in integrated circuits is the elevation of operating temperature. That is, as more power is consumed, the temperature of the integrated circuit rises. As a direct result of the increase in the temperature of the integrated circuit, various temperature dependent operational characteristics of transistors within the integrated circuit will change such that the overall effect is a reduced ability to operate at high frequency. Put more simply, as the temperature rises the integrated circuit tends to slow down.
In order to preserve the desired high speed operational characteristics for integrated circuits with relatively high power consumption, various power management and thermal management strategies have been adopted. One example of a power management technique is reducing the frequency of operations when the need for high speed operation is absent. In this way power consumption is reduced. One example of a thermal management technique is providing a thermally conductive pathway, such as a heatsink, with which to draw waste heat away from the integrated circuit. Indeed, heat sinks have become ubiquitous as a simple, cost effective mechanism for removing waste heat. Together, power management and thermal management techniques work to maintain the integrated circuit at a temperature low enough to achieve the desired high speed operation.
Before an integrated circuit reaches a customer, the integrated circuit manufacturer conducts a series a tests to verify that the integrated circuit operates according to some specification. A complex integrated circuit, such as a microprocessor, is typically tested first while it is still in wafer form, and then tested again after it is packaged. The testing of integrated circuits at the wafer level and packaged level is typically performed with a general purpose programmable tester. More recently, a requirement has arisen for these complex integrated circuits to be tested yet again in a system environment that closely emulates the environment in which these integrated circuits will actually be used. It is well-known in the field of integrated circuit testing that parameters such as the power supply voltage and the temperature of the integrated circuit must be controlled to achieve an appropriate confidence level in the test results. It is also well-known in the field of integrated circuit testing that increasing the time involved in testing an integrated circuit increases the costs of manufacturing.
What is needed are methods and systems for effectively testing complex integrated circuits in a system environment without consuming unnecessary amounts of time.